1. Field of the Invention
The present invention relates to non-volatile memory cells in push-pull configuration. More particularly, the present invention relates to non-volatile memory cells in push-pull configuration that may be employed in FPGA devices.
2. The Prior Art
Push-pull non-volatile memory cells for FPGAs have been previously proposed, as shown by illustrative examples in FIGS. 1 and 2. As shown in both FIGS. 1 and 2, a basic push-pull non-volatile memory cell for use in an FPGA device includes a non-volatile p-channel memory transistor 10 connected in series with a non-volatile n-channel memory transistor 12. The common drain connections of the non-volatile p-channel memory transistor 10 and the non-volatile n-channel memory transistor 12 are connected to the gate of a volatile n-channel switch transistor 14 that is used to selectively make connections between circuit nets in the FPGA depending on the state of the memory cell. The push-pull non-volatile memory cell shown in FIG. 1 employs separate floating gates for the non-volatile p-channel memory transistor 10 and the non-volatile n-channel memory transistor 12, as well a separate control gate lines for both devices. The push-pull non-volatile memory cell shown in FIG. 2 employs a common floating gate for both the non-volatile p-channel memory transistor 10 and the non-volatile n-channel memory transistor 12, and a common control gate line for both devices.
When non-volatile p-channel memory transistor 10 is turned off and non-volatile n-channel memory transistor 12 is turned on, there is a low voltage at the gate of volatile n-channel switch transistor 14, which remains turned off. Conversely, when non-volatile p-channel memory transistor 10 is turned on and non-volatile n-channel memory transistor 12 is turned off, there is a high voltage at the gate of volatile n-channel switch transistor 14, which is then turned on.
In order for volatile n-channel switch transistor 14 to pass a high logic signal of around 1.5V, the voltage on its gate must be in excess of 2.5 volts. When n-channel memory transistor 12 is turned off, its drain is at a voltage of between about 2.5V and 3.3V and its source is at 0V. When p-channel memory transistor 12 is turned off, its drain is at a voltage of between about 0V and about 0.5V and its source is at voltage such as 2.5V or 3.3V. Persons of ordinary skill in the art will observe that the one of non-volatile p-channel memory transistor 10 and non-volatile n-channel memory transistor 12 that is turned off in the push-pull memory cell must be designed to tolerate a Vds of more than 2.5V for a period greater than 20 years for the device to have an acceptable lifetime. For many non-volatile memory devices this can cause the off device to degrade over time.
Prior art patents disclose full push-pull non-volatile memory cells, however it is not believed that there is an actual product employing such a cell has not been reported.
There remains a need for a push-pull non-volatile memory cell in which the volatile n-channel switch transistor is able to pass a high logic signal of around 1.5V and in which the memory transistor that is turned off in the push-pull memory cell can tolerate a Vds of more than 2.5V over the lifetime of the device.